2021-09-02 23:11:11 索煒達(dá)電子 663
項(xiàng)目編號:E752
文件大?。?00K
源碼說明:帶中文注釋
開發(fā)環(huán)境:Verilog
簡要概述:
說明
測試平臺:友晶科技 DE-10開發(fā)板
軟件版本:Quartus 17.0
描述:使用IIC協(xié)議配置WM8731芯片為DAC輸出音頻模式,使用IIS協(xié)議傳輸播放的數(shù)據(jù)(單頻正弦信號),按鍵控制音量調(diào)節(jié),SW0開關(guān)控制復(fù)位,SW1開關(guān)控制靜音
目錄│文件列表:
└ WM8731_Audio
└ WM8731_Audio
│ c5_pin_model_dump.txt
│ DE10_Standard_golden_top.htm
│ DE10_Standard_golden_top.qpf
│ DE10_Standard_golden_top.qsf
│ DE10_Standard_golden_top.qws
│ DE10_Standard_golden_top.sdc
│ DE10_Standard_golden_top.v
│ DE10_Standard_golden_top_assignment_defaults.qdf
│ FPGAclean.bat
│ PLL_Audio.xml
├ IP_Core
│ │ PLL_Audio.bsf
│ │ PLL_Audio.cmp
│ │ PLL_Audio.ppf
│ │ PLL_Audio.qip
│ │ PLL_Audio.sip
│ │ PLL_Audio.spd
│ │ PLL_Audio.v
│ │ PLL_Audio_sim.f
│ ├ PLL_Audio
│ │ │ PLL_Audio_0002.qip
│ │ └ PLL_Audio_0002.v
│ └ PLL_Audio_sim
│ │ PLL_Audio.vo
│ ├ aldec
│ │ └ rivierapro_setup.tcl
│ ├ cadence
│ │ │ cds.lib
│ │ │ hdl.var
│ │ └ ncsim_setup.sh
│ ├ mentor
│ │ └ msim_setup.tcl
│ └ synopsys
│ ├ vcs
│ │ └ vcs_setup.sh
│ └ vcsmx
│ │ synopsys_sim.setup
│ └ vcsmx_setup.sh
├ output_files
│ │ DE10_Standard_golden_top.asm.rpt
│ │ DE10_Standard_golden_top.cdf
│ │ DE10_Standard_golden_top.done
│ │ DE10_Standard_golden_top.eda.rpt
│ │ DE10_Standard_golden_top.fit.rpt
│ │ DE10_Standard_golden_top.fit.smsg
│ │ DE10_Standard_golden_top.fit.summary
│ │ DE10_Standard_golden_top.flow.rpt
│ │ DE10_Standard_golden_top.jdi
│ │ DE10_Standard_golden_top.map.rpt
│ │ DE10_Standard_golden_top.map.smsg
│ │ DE10_Standard_golden_top.map.summary
│ │ DE10_Standard_golden_top.pin
│ │ DE10_Standard_golden_top.sld
│ │ DE10_Standard_golden_top.sof
│ │ DE10_Standard_golden_top.sta.rpt
│ │ DE10_Standard_golden_top.sta.summary
│ └ greybox_tmp
│ └ cbx_args.txt
├ Signal tap
│ └ stp1.stp
├ simulation
│ └ modelsim
│ │ DE10_Standard_golden_top.sft
│ │ DE10_Standard_golden_top.vo
│ └ DE10_Standard_golden_top_modelsim.xrf
└ V_File
│ Audio_Control.v
│ EDGE.v
│ IIC.v
│ IIS.v
│ KEY_DEBOUNCE.v
└ RESET.v